Certain semiconductor devices, e.g., magnetic random access memory (MRAM) devices, use magnetic memory cells to store information. Each magnetic memory cell typically comprises a submicron piece of magnetic material, e.g., having the dimensions of 300 nanometers (nm) by 600 nm in area and five nm thick.
Information is stored in such semiconductor devices as an orientation of the magnetization of a free layer in the magnetic memory cell as compared to an orientation of the magnetization of a fixed (e.g., reference) layer in the memory cell. The magnetization of the free layer may be oriented parallel or anti-parallel relative to the fixed layer, representing either a logic “1” or a “0.” The orientation of the magnetization of a given layer (fixed or free) may be represented by an arrow pointing either to the left or to the right. When the magnetic memory cell is sitting in a zero applied magnetic field, the magnetization of the magnetic memory cell is stable, pointing either left or right. The application of a magnetic field can switch the magnetization of the free layer from left to right, and vice versa, to write information to the magnetic memory cell. One of the important requirements for data storage is that the magnetization of the cell not change orientation unintentionally during the writing process or when there is a zero applied field, or only a small applied field.
Unfortunately, in practice, the magnetization of one or more magnetic memory cells may change orientation unintentionally, due, at least in part, to thermal activation. Thermal activation occurs when thermal energy from the environment surrounding a given cell overcomes an activation energy barrier so as to change the direction of magnetization of the magnetic memory cell. The occurrences of thermal activation should be minimized. The resulting error rate due to thermally activated switching is called the soft error rate (SER).
One of the objectives in designing semiconductor devices is to minimize the operating power and area consumed by the devices. These two design objectives, namely, low operating power and small area, may be achieved by devices having a low switching field to switch such devices. A low switching field uses a low switching current, which in turn uses less power. Further, lower switching currents require smaller switches, which occupy less area. Consequently, these two design objectives are consistent with one another. However, lowering switching fields often undesirably lead to an increase in the SER.
Therefore, techniques are needed for operating semiconductor devices with a low switching field, while at the same time reducing, or eliminating, the effect of soft errors.